The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a tungsten (W) line including a diffusion barrier layer.
As a linewidth of a dynamic random access memory (DRAM) device (e.g., a linewidth of a gate constituting a transistor) decreases under 100 nm, a sheet resistance (Rs) rapidly increases and a high-speed operation characteristic of the device is deteriorated due to a resistance-capacitance (RC) delay.
FIG. 1A is a top view of a gate structure constituting a wordline in a DRAM device. FIG. 1B illustrates variation of sheet resistance Rs according to a linewidth.
In the DRAM device, a bias is applied by connecting line-shaped gates to a number of memory cell regions formed by a shallow trench isolation (STI) process. Referring to FIG. 1A, a sheet resistance Rs change from a change in linewidth of a gate G is a parasitic resistance in a serial form.
Referring to FIG. 1B, the Rs of the gate G functioning as a parasitic resistance rapidly increases as the linewidth of the gate G decreases. When the gate G includes tungsten silicide (WSix), the Rs is higher and increases more rapidly as the linewidth of the gate G decreases.
As shown in FIG. 1B, when the gate G includes a tungsten (W), e.g., a tungsten nitride (WNX) layer, having a low resistivity than the tungsten silicide (WSiX) layer, the Rs may effectively decrease.
Recently, in memory devices having a linewidth under 0.1 μm, it is essential to use a W layer to form electrodes of a gate, a bit line and a metal line. A line structure using the W layer as an electrode is called a W line.
When the W line includes a polysilicon layer, it is required to form a diffusion barrier layer between the W layer and the polysilicon layer. This is to prevent an abnormal silicidation from occurring between the W layer and the polysilicon layer in a subsequent thermal treatment.
FIG. 2A illustrates contact resistances of a W layer changed according to the kinds of the diffusion barrier layers. Referring to FIG. 2A, the W line includes a polysilicon layer and a W layer. The polysilicon layer may include N-type impurities (N+ poly) or P-type impurities (P+ poly). The diffusion barrier layer may include one of a WN layer, a stack structure of WSix/WN layers, and a stack structure of titanium (Ti)/titanium nitride (TiN)/WN layers. The contact resistance means an interfacial resistance between the W layer and the polysilicon layer.
The W line including the WN layer as the diffusion barrier layer has a high contact resistance due to an insulative silicon (Si)—N reaction occurring at an interface of the WN layer and the polysilicon layer. In this case, the contact resistance is always high regardless of the kind of impurities doped into the polysilicon layer.
The W line including the stack structure of the WSix/WN layers has differing contact resistance depending on a type of impurities doped into the polysilicon layer. When the polysilicon layer is doped with P-type impurities, the contact resistance increases up to that of the W line including the WN layer. This is due to an insulative boron (B)—N reaction occurring at the interface of the polysilicon layer and the diffusion barrier layer. On the other hand, when the polysilicon layer is doped with N-type impurities, the contact resistance decreases.
When the W line includes the stack structure of the Ti/TiN/WN layers as the diffusion barrier layer, the contact resistance may be significantly lowered than the other diffusion barrier layers, regardless of the kind of the impurities doped into the polysilicon layer. This result is obtained because an insulative reaction does not occur at the interface of the polysilicon layer and the diffusion barrier layer.
FIG. 2B is a diagram showing sheet resistance of the W layer changed according to kinds of diffusion barrier layers.
In a W line including a stack structure of WSix/WN layers, the WN layer deposited on the amorphous WSix layer is amorphous. Accordingly, a W layer deposited on the WN layer has a large grain size and the W layer has a low sheet resistance.
On the other hand, in a W line including a stack structure of Ti/WN layers, the WN layer deposited on the crystalloid Ti layer has a crystalloid structure. Accordingly, in this case, the W layer deposited on the WN layer has a small grain size. As a result, the W layer has a high sheet resistance.
In a W line including a stack structure of TiN/WN layers, the W layer has a high sheet resistance due to the TiN layer deposited in the crystalloid form.
Table 1 shows the contact resistance and the sheet resistance according to the kind of diffusion barrier layers.
In Table 1, NMOS Rc represents a gate contact resistance of an NMOS transistor including a polysilicon layer doped with N-type impurities. PMOS Rc represents a gate contact resistance of a PMOS transistor including a polysilicon layer doped with P-type impurities. The NMOS Rc and the PMOS Rc show contact resistances when employing a process for forming a W dual gate.
TABLE 1WNWSix/WNTi/(TiN)/WNNMOS RcHighLowLowPMOS RcHighHighLowRsLowLowHigh
According to Table 1, there is no diffusion barrier layer which can obtain both low RS and low Rc (NMOS and PMOS).